1. Field of the Invention
This invention relates to the field of semiconductor logic gates having devices of different conductivity types.
2. Prior Art
The first integrated MOS circuits were developed in the early 1960's, though, at that time, processing techniques limited the production of these devices to primarily p-channel devices. The MOS transistor is a majority carrier device having a conducting channel through which current flows between a source and a drain which is modulated by a voltage applied to a gate. Further development brought forth complementary symmetry MOS devices (CMOS) which by a combination of features provided high noise immunity, ultra-low power consumption and good switching speeds. Basically, the CMOS device combines one p-channel MOS transistor and one n-channel MOS transistor both diffused on the same substrate. For example, if an n-substrate is used, then n-regions in p-wells are formed which become the source and drain regions of the n-channel transistor. In the fabrication process, channel stops or guard bands are added to limit inversion effects between an adjacent n-channel and p-channel.
In the CMOS inverter comprising a p- and an n-channel, since both devices cannot be on simultaneously, there is no through current (except during switching) and therefore, there is provided the desired ultra-low power consumption. Similarly in other circuits using CMOS devices in which there are as many n-channels as p-channels, there is extremely low power dissipation. However, with as many p-channels as n-channels when a circuit is implemented on a CMOS chip, there are many p-wells on an n-substrate and many channel stops or guard bands. Similarly, many n-wells are required with p-substrates. However, for purposes of simplicity in description, only n-substrates will be discussed. The designer of the chip is continuously effectively entering and exiting p-wells. Each time the designer goes into and out of a p-well a channel stop must be added and this takes up much room on the chip. Therefore, it is very desirable for the designer when he designs a p-well, to attempt to optimize the number of devices inside that p-well thereby to minimize the number of times he is required to come in and out of that p-well. In this way, he may obtain a significant real estate or area of geometry improvement in the layout on the chip. Of course, the optimum saving of real estate occurs in a single channel type of technology using either all n-channels or all p-channels. However, such single channel technology has not provided the important advantages of CMOS devices described above.